Da Greek posts on Rambus Inc. reexam

More from Da Greek's blog:

The fifth/sixth area of the specification that Samsung attacked in the reexamination requests is the language that calls for “sampling data on the transition of an external clock signal” and similarly that a first portion of data is sampled “in response to a rising edge” of such signal while a second portion of data is sampled “in response to a falling edge” of such signal. Since the issues are intertwined I am discussing them both together here.

Cutting to the chase . . .

If Rambus succeeds - as I believe it will on this point as well - the written description score will stand 6 – 0, and more importantly, their claims on DDR will be brought back from the precipice and put back into play.

Big dogs

Pat Choate, an economist, looked at seven corporations (Big Dogs) backing the Coalition for Patent Fairness (CPF): Intel, Dell, HP, Cisco, Oracle, Micron, and Apple.

His research is summarized at The Patent Prospector. Lots of interesting statistics, including this:

In the 11-year period 1996-2006, the seven CPF founding corporations disclosed $1.9 billion in patent settlement payments, an average of $173 million per year. During that same time, these seven corporations had collective revenues of more than $1.7 trillion.

Patent reform, protecting the strong?

The Register interviewed Steve Perlman (WebTV, owner of 70+/- patents) about Patent Reform Act. A very interesting article.

"This is isn't pharm versus high-tech," he said. "This is people who need patents versus people who don't need patents."

The comments that follow are equally interesting.

Remember that the courts do have most of the facts and they are hosing members of the Coalition for Patent fairness & PIRACY. These companies are the worst which America has produced. They act like school yard bullies, picking on those who are weak, and then when they get their justly earned attitude adjustments they rationalize and whine like like children who have not yet learned the difference between right and wrong.

Ronald J. Riley,

President - www.PIAUSA.org - RJR at PIAUSA.org

Executive Director - www.InventorEd.org - RJR at InvEd.org

Senior Fellow - www.PatentPolicy.org - RRiley at PatentPolicy.org

Rambus Inc. patents

The egg, as is zero this week.

HT FinzToRite.

Rambus Inc. & Ware et al. patents, but "ware" is the restatement?

United States Patent 7,225,311
Ware, et al. May 29, 2007

Method and apparatus for coordinating memory operations among diversely-located memory components

A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data using a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.

Inventors: Ware; Frederick A. (Los Altos, CA), Tsern; Ely K. (Los Altos, CA), Perego; Richard E. (San Jose, CA), Hampel; Craig E. (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/732,533
Filed: December 11, 2003

***

United States Patent 7,225,292
Ware, et al. May 29, 2007

Memory module with termination component

Abstract
A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal path is coupled to each of the memory devices and the termination component, and extends along the memory devices such that signals propagating on the control signal path propagate past each of the memory devices in succession before reaching the termination component. A unique set of data signal paths is coupled to each of the memory devices.

Inventors: Ware; Frederick A. (Los Altos, CA), Tsern; Ely K. (Los Altos, CA), Perego; Richard E. (San Jose, CA), Hampel; Craig E. (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/219,096
Filed: September 1, 2005

Submitted by FinzToRite.

Rambus Inc., a couple more patents

United States Patent 7,222,224
Woo, et al. May 22, 2007

System and method for improving performance in computer memory systems supporting multiple memory access latencies

Abstract
A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest latency regions of physical memory.

Inventors: Woo; Steven C. (Saratoga, CA), Tsang; Brian H. (East Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/850,803
Filed: May 21, 2004

***

United States Patent 7,222,209
Garlepp, et al. May 22, 2007

Expandable slave device system

Abstract
A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

Inventors: Garlepp; Bruno W. (Austin, TX), Barth; Richard M. (Ashland, OR), Donnelly; Kevin S. (Los Altos, CA), Tsern; Ely K. (Los Altos, CA), Hampel; Craig E. (San Jose, CA), Mitchell; Jeffrey D. (Santa Clara, CA), Gasbarro; James A. (Fox Chapel, PA), Garrett, Jr.; Billy W. (Mountain View, CA), Ware; Fredrick A. (Los Altos Hills, CA), Perino; Donald V. (North Potomac, MD)
Assignee: Rambus, Inc. (Los Altos, CA)
Appl. No.: 10/738,293
Filed: December 16, 2003

Submitted by FinzToRite.

Rambus Inc. hatching patents

United States Patent 7,219,205
Ware May 15, 2007

Memory controller device

Abstract
A memory controller device. The memory controller includes a first circuit to capture a first bit of data in response to a rising edge of a strobe signal and a second circuit to capture a second bit of data in response to a falling edge of the strobe signal. The memory controller device also includes a first register circuit coupled with the first circuit where, in operation, the first register circuit samples the first bit of data from the first circuit in response to a clock signal and is adjustable to select which transition of the clock signal is employed to sample the first bit of data. The memory controller device additionally includes a second register circuit coupled with the second circuit. The second register circuit, in operation, samples the second bit of data from the second circuit in response to the clock signal and is adjustable to select which transition of the clock signal is employed to sample the second bit of data.

Inventors: Ware; Frederick A. (Los Altos Hills, CA)
Assignee: Rambus, Inc. (Mountain View, CA)
Appl. No.: 10/893,206
Filed: July 16, 2004

HT FinzToRite.

Rambus Inc. lands two more patents

United States Patent 7,216,187
Perego, et al. May 8, 2007

Memory system including a circuit to convert between parallel and serial bits

Abstract
A memory controller comprises a circuit to convert a set of parallel constituent bits to a serial stream of constituent bits. A first output driver receives at least four bits of the serial stream of constituent bits in succession from the circuit. The first output driver outputs the at least four bits of the serial stream of constituent bits onto a first external signal line.

Inventors: Perego; Richard E. (San Jose, CA), Ware; Fredrick A. (Los Altos Hills, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/151,792
Filed: June 14, 2005


United States Patent 7,215,161
Nguyen May 8, 2007

Wave shaping output driver to adjust slew rate and/or pre-emphasis of an output signal

Abstract
Integrated circuit, system, method and machine readable media embodiments adjust a slew rate and/or a transmit pre-emphasis of an output signal at selected phases during a bit time. A timing circuit provides a plurality of delayed data signals in response to a clock signal. A plurality of adjustable impedance circuits, including a plurality of select circuits, output a plurality of selected delayed data signals to form the output signal having an adjusted slew rate. Delay elements in the timing circuit are also biased from a current of a lock loop circuit to further adjust slew rate of the output signal. Transmit pre-emphasis of the output signal is adjusted by selecting a polarity of a selected delayed data signal in each of the plurality of adjustable impedance circuits. Each adjustable impedance circuit also includes a predriver and driver for adjusting impedance in response to a signal indicating an impedance value. In an embodiment, an integrated circuit is able to operate in multiple modes of operation depending upon the type of output signal, frequency range of the output signal, physical packaging and/or system configuration.

Inventors: Nguyen; Huy (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/068,116
Filed: February 28, 2005

HT FinzToRite.

Rambus Inc., more gas in the tank

United States Patent 7,213,121
Barth, et al. May 1, 2007

Memory device having asynchronous/synchronous operating modes

Abstract
An integrated circuit memory device comprises a memory array to store data, a circuit to output the data at a pin, and a register to store a value that indicates a mode of operation of the integrated circuit memory device. The mode of operation is selected from at least one of a synchronous mode of operation and an asynchronous mode of operation. During the synchronous mode of operation, the circuit outputs the data in response to a transition of an external clock signal. During the asynchronous mode of operation, the circuit outputs the data after a period of time from when a transition of an external control signal is detected.

Inventors: Barth; Richard Maurice (Palo Alto, CA), Horowitz; Mark Alan (Palo Alto, CA), Hampel; Craig Edward (San Jose, CA), Ware; Frederick Abbot (Los Altos Hills, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/123,931
Filed: May 6, 2005

HT FinzToRite.

Rambus Inc. adds to patent portfolio

April 24, 2007, the United States Patent Office issued four new patents to Rambus Inc. Rambus states:

For over fifteen years, Rambus has been guided by a fundamental commitment to advanced research and development. Rambus engineers invented technology that is foundational to nearly all modern digital electronic devices.

Read FAQ about Rambus licensing.

United States Patent 7,209,397
Ware, et al. April 24, 2007

Memory device with clock multiplier circuit

Abstract
A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory device includes a data receive circuit to receive data at the frequency of the second clock signal and may also include a data transmit circuit to transmit data at the frequency of the second clock signal. Further, the clock generating circuit may additionally generate a third clock signal having a third frequency that is also a multiple of the first frequency, the third clock signal being supplied to a control circuit of the memory device to time the reception of control and/or address signals therein. In a particular embodiment the second frequency is a four-times or eight-times multiple of the first frequency, and the third frequency is a two-times multiple of the first frequency.

Inventors: Ware; Frederick A. (Los Altos, CA), Tsern; Ely K. (Los Altos, CA), Perego; Richard E. (San Jose, CA), Hampel; Craig E. (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/094,137
Filed: March 31, 2005

United States Patent 7,209,997
Farmwald, et al. April 24, 2007

Controller device and method for operating same

Abstract
A controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The output driver circuitry may output a value, a first operation code, a block size value, and second operation code. The first operation code may represent an instruction to a memory device to store the value in a register in the memory device. The block size value may indicate an amount of read data to be output by the memory device in response to the second operation code. The second operation code may represent an instruction to the memory device to perform a read operation. The input receiver circuitry may sample a first portion of the read data output by the memory device after a read delay following the outputting of the second operation code.

Inventors: Farmwald; Michael (Berkeley, CA), Horowitz; Mark (Palo Alto, CA) Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/716,596
Filed: November 20, 2003

United States Patent 7,210,015
Barth, et al. April 24, 2007

Memory device having at least a first and a second operating mode

Abstract
An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.

Inventors: Barth; Richard Maurice (Palo Alto, CA), Horowitz; Mark Alan (Palo Alto, CA), Hampel; Craig Edward (San Jose, CA), Ware; Frederick Abbot (Los Altos Hills, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/153,679
Filed: June 15, 2005

United States Patent 7,210,016
Ware, et al. April 24, 2007

Method, system and memory controller utilizing adjustable write data delay settings

Abstract
A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Inventors: Ware; Frederick A. (Los Altos, CA), Tsern; Ely K. (Los Altos, CA), Perego; Richard E. (San Jose, CA), Hampel; Craig E. (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/281,184
Filed: November 15, 2005

HT FinzToRite.
HT Rambus Inc. engineers

Rambus Inc. racks another patent

United States Patent 7,190,754
Chang, et al. March 13, 2007

Transceiver with selectable data rate

Abstract
An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal. A select circuit selects, according to a transmit data rate select signal, data bits within an outbound data value to form the parallel set of bits received within the serializing circuit. Bits within the outbound data value are selected to achieve a first data rate when the transmit data rate select signal is in a first state, and to achieve a second data rate when the transmit data rate select signal is in a second state.

Inventors: Chang; Kun-Yung K. (Los Altos, CA), Donnelly; Kevin S. (Los Altos, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/026,371
Filed: December 24, 2001

HT FinzToRite.

Rambus Inc. patents delay?

FinzToRite, in the midst of his weekly patent search, discovered that Rambus Inc. has two new patents. The first by Dally, et al. It struck FTR that Rambus had done it - they had patented dallying. Not only was Rambus Inc. giving its own shareholders the proverbial middle finger, it was patenting the process!

FTR, shook his head and his vision cleared . . .

United States Patent 7,187,721
Dally, et al. March 6, 2007

Transition-time control in a high-speed data transmitter

Abstract
Transition time of a data signal is controlled by applying different delays to the data signal and combining the delayed data signals. The transition time of the data output is determined by difference in delays applied to the data input and may be proportional to bit time of the bit clock. The data input may be applied directly to the delay elements or may be clocked by clock signals delayed by the delay elements. The delayed data is applied to parallel driver circuits. Supply voltage to the delay elements can be controlled to compensate for production and environmental variations. The supply voltage controller includes parallel delay elements of different delays and a phase comparator, the output of which controls the supply voltage applied to the delay elements.

Inventors: Dally; William J. (Stanford, CA), Poulton; John W. (Chapel Hill, NC)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 09/557,164
Filed: April 25, 2000

***

United States Patent 7,187,572
Perego, et al. March 6, 2007

Early read after write operation memory device, system and method

Abstract
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment. The memory device includes an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

Inventors: Perego; Richard E. (San Jose, CA), Ware; Frederick A. (Los Altos Hills, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/353,405
Filed: January 29, 2003

HT FinzToRite.

Patent continuation restrictions - undead

The Patent Prospector reports that patent continuation and divisional restrictions are now "undead". This a couple of days after the whispered post mortem. Expect that the patent bar will rally and mount an assault.

Patent reform, well no

Digit reports that close to 300 people, including tech executives, advocacy groups and government officials were expected to attend the Tech Policy Summit this week in San Jose, California.

Patent reforms, trolls and the PTO backlog graced the menu. Adding to the indigestion was Deborah Platt Majoras, chairman of the U.S. Federal Trade Commission, who endorses the idea of post-patent review. (Any Donkey wonders if Ms. Majoras wants to add the post-patent review to her ever-expanding portfolio.)

The Patent Prospector repeats the gossip that USPTO Under Secretary Jon Dudas recently assured tech leaders that proposed continuation limits are as "dead as a doornail." Add Treowth to the gossip chain.

Rambus Inc. patents, it's a two-fer

United States Patent 7,184,483
Rajan February 27, 2007

Technique for emulating differential signaling

Abstract
A technique for emulating differential signaling is disclosed. In one exemplary embodiment, the technique is realized by encoding a plurality of input signals so as to generate a plurality of encoded signals having a spatial run length of N, wherein N is an integer having a value of at least two. Each of the plurality of encoded signals is then transmitted over a transmission medium so as to provide a respective plurality of transmitted encoded signals. Each of the plurality of transmitted encoded signals is then compared with at least N neighboring others of the plurality of transmitted encoded signals so as to recover a representation of each of the plurality of encoded signals. Each of the plurality of recovered encoded signals is then decoded so as to generate a plurality of decoded signals representing the plurality of input signals.
Inventors: Rajan; Suresh (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/326,343
Filed: January 6, 2006

***

United States Patent 7,183,805
Wang , et al. February 27, 2007

Method and apparatus for multi-mode driver
Abstract
Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.
Inventors: Wang; Yueyong (Sunnyvale, CA), Daly; Barry W. (Sunnyvale, CA), Nguyen; Nhat M. (San Jose, CA), Frans; Yohan U. (Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/385,234
Filed: March 20, 2006

Hat tip FinzToRite.

Rambus Inc., still chopping wood

And storing it for the winter . . .

United States Patent 7,174,400
Horowitz, et al. February 6, 2007

Integrated circuit device that stores a value representative of an equalization co-efficient setting

Abstract
An integrated circuit device is described. The integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device.

Inventors: Horowitz; Mark A. (Menlo Park, CA), Barth; Richard M. (Palo Alto, CA), Hampel; Craig E. (San Jose, CA), Moncayo; Alfredo (Redwood City, CA), Donnelly; Kevin S. (Los Altos, CA), Zerbe; Jared L. (Woodside, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/181,411
Filed: July 13, 2005

HT FinzToRite for the link.

Rambus Inc., patent hat trick

United States Patent 7,171,528
Evans, et al. January 30, 2007

Method and apparatus for generating a write mask key

Abstract
A method and apparatus provides a mask key that is used instead of mask data. In an embodiment of the present invention, a write mask key is generated by a memory controller and transferred to a memory device that uses the write mask key to determine whether to write a data value to a storage array. A plurality of decoders, an OR logic gate tree and a binary propagation tree is used to provide the write mask key that reduces latency while using the approximate same circuit area and allows for the use of standard software tools in an embodiment of the present invention. A plurality of log.sub.2 decoders is coupled to a plurality of OR logic gates in the OR logic gate tree.

Inventors: Evans; Marc (San Jose, CA), Perego; Richard E. (Thornton, CO), Ware; Frederick A. (Los Altos Hills, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/896,167
Filed: July 21, 2004

***

United States Patent 7,171,321
Best January 30, 2007

Individual data line strobe-offset control in memory systems

Abstract
Systems and methods for strobe signal timing calibration and control in strobe-based memory systems are provided below. These strobe-offset control systems and methods receive a strobe signal from a memory device and in turn automatically generate separate per-bit strobe signals for use in receiving data on each data line of a memory system. The systems/methods generate the optimal per-bit strobe signals by automatically calibrating per-bit offset timing between data signals of individual data bits and corresponding strobe signals. The strobe-offset control system effectively removes the detected phase difference between the data signal and the strobe signal.

Inventors: Best; Scott C. (Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/923,421
Filed: August 20, 2004

***

United States Patent 7,170,314
Haba, et al. January 30, 2007

Multiple channel modules and bus systems using same

Abstract
Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Inventors: Haba; Belgacem (Cupertino, CA), Perego; Richard E. (San Jose, CA), Nguyen; David (San Jose, CA), Garrett, Jr.; Billy W. (Mountain View, CA), Tsern; Ely (Los Altos, CA), Hampel; Crag E. (San Jose, CA), Yip; Wai-Yeng (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/054,955
Filed: February 11, 2005

HT FinzToRite for the links.

Find your own hat stamp and other cool stuff at Frantic Stamper.

Rambus Patent

United States Patent 7,151,390
Nguyen, et al. December 19, 2006

Calibration methods and circuits for optimized on-die termination

Abstract
Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Inventors: Nguyen; Huy M. (San Jose, CA), Gadde; Vijay (Cupertino, CA), Lau; Benedict (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 11/100,949

Filed: April 6, 2005

HT FinzToRite.

Rambus Inc. patents - counting chickens

We've heard it, read it, and even said it - "Don't count your chickens until they hatch." However, here at Treowth, we dutifully count each Rambus Inc. patent . . . if you would like to practice counting chickens, ducks and elephants, follow this link to the LearningPlanet.com.

United States Patent 7,149,856
Garlepp, et al. December 12, 2006

Method and apparatus for adjusting the performance of a synchronous memory system

Abstract
A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.

Inventors: Garlepp; Bruno Werner (Mountain View, CA), Chau; Pak Shing (San Jose, CA), Donnelly; Kevin S. (San Fransisco, CA), Portmann; Clemenz (Cupertino, CA), Stark; Donald C. (Los Altos, CA), Sidiropoulos; Stefanos (Stanford, CA), Barth; Richard M. (Palo Alto, CA), Davis; Paul G. (San Jose, CA), Tsern; Ely K. (Los Altos, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 10/386,210

Filed: March 10, 2003

***

United States Patent 7,148,699
Stark December 12, 2006

Technique for calibrating electronic devices

Abstract
A technique for calibrating a second electronic device using a first electronic device having a reference characteristic is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for calibrating a second electronic device using a first electronic device, wherein the first electronic device has a reference characteristic, wherein the second electronic device has an adjustable element, and wherein the first electronic device and the second electronic device are interconnected via one or more signal lines. The method comprises generating a first value based at least in part upon the reference characteristic, and providing the first value to the second electronic device via one of the one or more signal lines. The method also comprises generating a second value, based at least in part upon the first value, using the adjustable element. The method further comprises comparing the second value to the first value, and adjusting the adjustable element so as to modify the second value until the second value substantially matches the first value.

Inventors: Stark; Donald C. (Los Altos Hills, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 10/298,541

Filed: November 19, 2002

As always, thanks to FinzToRite for patent links.

Rambus Inc. new patents issued?

It is an egg week . . .

HT, FinzToRite.