Rambus Inc. adds to patent portfolio

April 24, 2007, the United States Patent Office issued four new patents to Rambus Inc. Rambus states:

For over fifteen years, Rambus has been guided by a fundamental commitment to advanced research and development. Rambus engineers invented technology that is foundational to nearly all modern digital electronic devices.

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United States Patent 7,209,397
Ware, et al. April 24, 2007

Memory device with clock multiplier circuit

Abstract
A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory device includes a data receive circuit to receive data at the frequency of the second clock signal and may also include a data transmit circuit to transmit data at the frequency of the second clock signal. Further, the clock generating circuit may additionally generate a third clock signal having a third frequency that is also a multiple of the first frequency, the third clock signal being supplied to a control circuit of the memory device to time the reception of control and/or address signals therein. In a particular embodiment the second frequency is a four-times or eight-times multiple of the first frequency, and the third frequency is a two-times multiple of the first frequency.

Inventors: Ware; Frederick A. (Los Altos, CA), Tsern; Ely K. (Los Altos, CA), Perego; Richard E. (San Jose, CA), Hampel; Craig E. (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/094,137
Filed: March 31, 2005

United States Patent 7,209,997
Farmwald, et al. April 24, 2007

Controller device and method for operating same

Abstract
A controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The output driver circuitry may output a value, a first operation code, a block size value, and second operation code. The first operation code may represent an instruction to a memory device to store the value in a register in the memory device. The block size value may indicate an amount of read data to be output by the memory device in response to the second operation code. The second operation code may represent an instruction to the memory device to perform a read operation. The input receiver circuitry may sample a first portion of the read data output by the memory device after a read delay following the outputting of the second operation code.

Inventors: Farmwald; Michael (Berkeley, CA), Horowitz; Mark (Palo Alto, CA) Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/716,596
Filed: November 20, 2003

United States Patent 7,210,015
Barth, et al. April 24, 2007

Memory device having at least a first and a second operating mode

Abstract
An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.

Inventors: Barth; Richard Maurice (Palo Alto, CA), Horowitz; Mark Alan (Palo Alto, CA), Hampel; Craig Edward (San Jose, CA), Ware; Frederick Abbot (Los Altos Hills, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/153,679
Filed: June 15, 2005

United States Patent 7,210,016
Ware, et al. April 24, 2007

Method, system and memory controller utilizing adjustable write data delay settings

Abstract
A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Inventors: Ware; Frederick A. (Los Altos, CA), Tsern; Ely K. (Los Altos, CA), Perego; Richard E. (San Jose, CA), Hampel; Craig E. (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/281,184
Filed: November 15, 2005

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HT Rambus Inc. engineers