Tuesday, May 22, 2007

Rambus Inc., a couple more patents

United States Patent 7,222,224
Woo, et al. May 22, 2007

System and method for improving performance in computer memory systems supporting multiple memory access latencies

A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest latency regions of physical memory.

Inventors: Woo; Steven C. (Saratoga, CA), Tsang; Brian H. (East Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/850,803
Filed: May 21, 2004


United States Patent 7,222,209
Garlepp, et al. May 22, 2007

Expandable slave device system

A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

Inventors: Garlepp; Bruno W. (Austin, TX), Barth; Richard M. (Ashland, OR), Donnelly; Kevin S. (Los Altos, CA), Tsern; Ely K. (Los Altos, CA), Hampel; Craig E. (San Jose, CA), Mitchell; Jeffrey D. (Santa Clara, CA), Gasbarro; James A. (Fox Chapel, PA), Garrett, Jr.; Billy W. (Mountain View, CA), Ware; Fredrick A. (Los Altos Hills, CA), Perino; Donald V. (North Potomac, MD)
Assignee: Rambus, Inc. (Los Altos, CA)
Appl. No.: 10/738,293
Filed: December 16, 2003

Submitted by FinzToRite.

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