Rambus rocks . . . ah yes, coffee is hitting the bloodstream . . .
United States Patent 7,062,597
Perego, et al. June 13, 2006
Integrated circuit buffer device
Abstract
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
Inventors: Perego; Richard E. (San Jose, CA); Sidiropoulos; Stefanos (Palo Alto, CA); Tsern; Ely (Los Altos, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 625276
Filed: July 23, 2003
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United States Patent 7,061,406
Dally, et al. June 13, 2006
Low power, DC-balanced serial link transmitter
Abstract
A transmitter for a data communication system that comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular signaling cell, and integrating for a second interval with a negative polarity within the particular signaling cell, to produce output representing the codewords. A sense circuit produces an output data stream.
Inventors: Dally; William J. (Palo Alto, CA); Poulton; John W. (Chapel Hill, NC)
Assignee: Rambus, Inc. (Los Altos, CA)
Appl. No.: 040835
Filed: January 21, 2005
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United States Patent 7,061,273
Wang, et al. June 13, 2006
Method and apparatus for multi-mode driver
Abstract
Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.
Inventors: Wang; Yueyong (Sunnyvale, CA); Daly; Barry W. (Sunnyvale, CA); Nguyen; Nhat M. (San Jose, CA); Frans; Yohan U. (Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 456303
Filed: June 6, 2003
Hat tip FinzToRite for the links.
Tuesday, June 13, 2006
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