Rambus patent quartet

United States Patent 7,003,639

Tsern, et al. February 21, 2006

Memory controller with power management logic

Abstract
A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.

Inventors: Tsern; Ely K. (Los Altos, CA); Satagopan; Ramprasad (San Jose, CA); Barth; Richard M. (Ashland, OR); Woo; Steven C. (Saratoga, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 873670

Filed: June 21, 2004

***

United States Patent 7,003,618

Perego, et al. February 21, 2006

System featuring memory modules that include an integrated circuit buffer devices

Abstract
A computer system includes a controller device having an interface disposed on a circuit board. A first socket is disposed on the circuit board and receives a first memory module having a first integrated circuit buffer device. The first memory module has a first plurality of integrated circuit memory devices coupled to the first integrated circuit buffer device. A first point-to-point link is coupled to the interface of the controller device. When the first memory module is received by the first socket, the first integrated circuit buffer device receives control information, address information, and data from the controller device over the first point-to-point link. A second socket is disposed on the circuit board and receives a second memory module having a second integrated circuit buffer device. The second memory module has a second plurality of memory devices coupled to the second integrated circuit buffer device. When the first and second memory modules are received by the first and second sockets, the second integrated circuit buffer device receives the data, the control information and the address information from the first integrated circuit buffer device over a second point-to-point link.

Inventors: Perego; Richard E. (San Jose, CA); Sidiropoulos; Stefanos (Palo Alto, CA); Tsern; Ely (Los Altos, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 078244

Filed: March 11, 2005

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United States Patent 7,002,500

Li, February 21, 2006

Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy

Abstract
A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter ("DAC") that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.

Inventors:
Li; Yingxuan (Cupertino, CA)

Assignee:Rambus Inc. (Los Altos, CA)

Appl. No.:114326

Filed:April 26, 2005

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United States Patent 7,002,367

Yu, et al. February 21, 2006

Method and apparatus for low capacitance, high output impedance driver

Abstract
An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Inventors:Yu; Leung (Santa Clara, CA); Vu; Roxanne T. (San Jose, CA); Lau; Benedict C. (San Jose, CA); Nguyen; Huy M. (San Jose, CA); Gasbarro; James A. (Pittsburgh, PA)

Assignee:Rambus, Inc. (Los Altos, CA)

Appl. No.: 349403

Filed:January 21, 2003

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Quartet courtesy of harmonize.com.