Rambus Patents - "Two-fer"

United States Patent 6,988,044

Batra, et al. January 17, 2006

Bus line current calibration

Abstract
Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

Inventors: Batra; Pradeep (Santa Clara, CA); Rutkowski; Rick A. (Sunnyvale, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 409033

Filed: April 8, 2003

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United States Patent: 6,987,823

Stark, et al. January 17, 2006

System and method for aligning internal transmit and receive clocks

Abstract
A circuit defining a second system clock in a system comprising a master connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master. The circuit comprising a delay locked loop circuit configured to receive the first system clock and a second phase feedback signal as inputs and to generate a transmit clock signal. A 90 degrees block configured to receive the transmit system clock and to generate a 90 degrees phased shifted version of the transmit clock signal. An output driver circuit configured to receive the 90 degrees phased shifted version of the transmit clock signal and to generate the second system clock. A first phase detector configured to receive a receive system clock and the transmit system clock and to generate a first phase feedback signal. A delay element configured to receive the first system clock and the first phase feedback signal and to generate a delayed first system clock. A second phase detector configured to receive the delayed first system clock and the second system clock and to generate the second phase feedback signal.

Inventors: Stark; Donald C. (Los Altos Hills, CA); Kim; Jun (Redwood City, CA); Sidiropoulos; Stefanos (Palo Alto, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 499025

Filed: February 7, 2000

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