Rambus Patent Hat Trick

United States Patent 6,976,114

Ware, December 13, 2005

Method and apparatus for simultaneous bidirectional signaling in a bus topology

Abstract
A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a transmit buffer is preferably provided for every other device on the bus with which it will communicate. One or more logic circuits, for example, a scheduler, is provided to coordinate exchange transactions between pairs of devices. Time delays are preferably provided between exchange transactions of different device pairs so as to prevent interference. Coherency checking is preferably implemented to avoid discrepancies introduced by information being held in a buffer pending an exchange transaction. Devices coupled to a common bus preferably maintain a transmit buffer for each other device on the bus with which they will be communicating. When one of the transmit buffers for communicating between a pair of devices contains an amount of data, that pair of devices is granted an exchange slot on the bus that provides a period of time during which the pair of devices may conduct their exchange transaction and communicate with each other over the bus. During the exchange slot, the pair of devices transfer information from their transmit buffers across the bus to receive buffers of the opposite device. Different exchange slots are used for different pairs of devices.
Inventors: Ware; Frederick A. (Los Altos, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 770996

Filed: January 25, 2001

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United States Patent 6,975,956

Chang, et al. December 13, 2005

Multiple sweep point testing of circuit devices

Abstract
An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

Inventors: Chang; Timothy C. (Saratoga, CA); Stark; Donald C. (Los Altos Hills, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 247188

Filed: September 19, 2002

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United States Patent 6,975,558

Farmwald, et al. December 13, 2005

Integrated circuit device

Abstract
An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control information and address information, wherein the control information specifies a write operation and the address information specifies a location within a memory array for the write operation. The integrated circuit device may also comprise a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 939500

Filed: September 14, 2004

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Hat tip - FinzToRite for the research.

Hat tip to yourkitchen.com for the photograph.