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United States Patent 6,952,431

Dally, et al. October 4, 2005

Clock multiplying delay-locked loop for data communications

Abstract
In a communications system, data is multiplexed onto a transmission medium at a transmitter and demultiplexed from the transmission medium at a receiver. The clock applied to the transmitter and receiver is a multiplying delay-locked loop in which a delay line provides a multiplied clock which is applied back to its input. A delay adjustment circuit including a proportional phase comparator of low offset adjusts delay in the delay line.

Inventors: Dally; William J. (Stanford, CA); Poulton; John W. (Chapel Hill, NC)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 557640

Filed: April 25, 2000

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