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United States Patent 6,952,123

Kizer, et al. October 4, 2005

System with dual rail regulated locked loop

Abstract
An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and one of a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Inventors: Kizer; Jade M. (Mountain View, CA); Lau; Benedict C. (San Jose, CA); Hampel; Craig E. (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 374252

Filed: February 25, 2003

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