Tuesday, September 27, 2005

"O" for the month - Not



United States Patent: 6,950,956

Zerbe, et al. September 27, 2005

Integrated circuit with timing adjustment mechanism and method

Abstract
An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Inventors: Zerbe; Jared LeVan (Woodside, CA); Donnelly; Kevin S. (Los Altos, CA); Sidiropoulos; Stefanos (Palo Alto, CA); Stark; Donald C. (Los Altos, CA); Horowitz; Mark A. (Menlo Park, CA); Yu; Leung (Los Altos, CA); Vu; Roxanne (San Jose, CA); Kim; Jun (Redwood City, CA); Garlepp; Bruno W. (Sunnyvale, CA); Ho; Tsyr-Chyang (San Jose, CA); Lau; Benedict Chung-Kwong (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 700655

Filed: November 3, 2003

Hat tip to FinzToRite of the Pinehurst Thread for the link.

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