It is a "two-fer" September

United States Patent: 6,949,958

Zerbe, et al. September 27, 2005

Phase comparator capable of tolerating a non-50% duty-cycle clocks

Abstract
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Inventors: Zerbe; Jared LeVan (Palo Alto, CA); Ching; Michael Tak-kei (Sunnyvale, CA); Abhyankar; Abhijit M. (Sunnyvale, CA); Barth; Richard M. (Palo Alto, CA); Chan; Andy Peng-Pui (San Jose, CA); Davis; Paul G. (San Jose, CA); Stonecypher; William F. (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 282531

Filed: October 28, 2002

Hat tip to FinzToRite of the Pinehurst Thread for the link.