Rambus will announce on Wednesday a new Terabyte Bandwidth Initiative (TBI) designed to bring terabyte bandwidth to future many-core architectures. The design places 16 DRAM channels, each operating at 16 Gbps with 4 bytes of data per clock. In theory, the total aggregate memory throughput would be 1,024 Gigabytes (1 Terabyte) available via sixteen separate channels, each of which could be piped directly to a group of multiple cores.HT Rambus Inc. for playing the media. Read the TG Daily for an informative article.
HT FTR for the link.
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