Rambus Inc. scores fünf patents

United States Patent 7,137,048
Zerbe, et al. November 14, 2006

Method and apparatus for evaluating and optimizing a signaling system

Abstract
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Inventors: Zerbe; Jared (Woodside, CA), Chau; Pak Shing (San Jose, CA), Stonecypher; William Franklin (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 09/976,170

Filed: October 12, 2001

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United States Patent 7,136,949
Hampel November 14, 2006

Method and apparatus for position dependent data scheduling

Abstract
A method and apparatus for position dependent data scheduling for communication of data for different domains along a bus is provided. Having an awareness of the relative position of different domains along a bus, one embodiment of the present disclosure schedules bus operations to allow data from multiple bus operations to be simultaneously present on the bus while preventing interference among the data. The present disclosure is compatible with buses having a termination on one end and those having terminations on both ends. In accordance with one embodiment of the present disclosure, bus operations are scheduled so that first data of a first bus operation involving a first domain are not present at domains involved in a second bus operation at times that would result in interference with second data of the second bus operation.

Inventors: Hampel; Craig (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 11/076,867

Filed: March 11, 2005

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United States Patent 7,136,310
Kasamsetty November 14, 2006

Programmable output driver turn-on time for an integrated circuit memory device

Abstract
An integrated circuit memory device, system and method turns on an output driver in response to a stored value that represents an amount of time from when the output driver is in an operational state to when the output driver begins to output valid read data in various embodiments. An output driver outputs valid read data after a settling amount of time. The sum of the amount of time from when the memory device receives a read command to when the output driver is turned-on and the settling amount of time, is approximately the time from receiving the read command, to at least beginning to provide valid read data at the output of the integrated circuit memory device. A read command is provided to the integrated circuit memory device by a memory controller. In an embodiment, the memory controller also provides or programs the value that represents the amount of time from when the output driver is in an operational state to when the output driver begins to output valid read data.
Inventors: Kasamsetty; Kishore (Cupertino, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 11/023,274

Filed: December 27, 2004

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United States Patent 7,135,925
Poulton November 14, 2006

Adaptive bias scheme for high-voltage compliance in serial links

Abstract
A high-speed serial-link driver transmits a differential data signal to a conventional differential receiver via a differential channel. The driver employs termination voltages that are high, relative to the supply voltage employed by the transmitter core logic, to support communication with legacy devices. Cascode amplifiers using an adaptive biasing scheme allow the driver to include voltage-sensitive, high-performance transistors despite the relatively high termination voltage.

Inventors: Poulton; John W. (Chapel Hill, NC)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 11/004,343

Filed: December 3, 2004

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United States Patent 7,135,903
Kizer, et al. November 14, 2006

Phase jumping locked loop circuit

Abstract
A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

Inventors: Kizer; Jade M. (Mountain View, CA), Lau; Benedict C. (San Jose, CA), Vu; Roxanne T. (San Jose, CA), Nguyen; Huy M. (San Jose, CA), Yu; Leung (Santa Clara, CA), Chou; Adam Chuen-Huei (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 10/374,251

Filed: February 25, 2003

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