Rambus Inc. patent hat trick

United States Patent 7,134,101

Liaw, et al. November 7, 2006

Active impedance compensation

Abstract
Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.

Inventors: Liaw; Haw-Jyh (Fremont, CA), Perino; Donald V. (Los Altos, CA), Chau; Pak Shing (San Jose, CA), Donnelly; Kevin S. (Los Altos, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 10/346,859

Filed: January 16, 2003

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United States Patent 7,133,945

Lau November 7, 2006

Scalable I/O signaling topology using source-calibrated reference voltages

Abstract
An embodiment of the invention is a scalable I/O interface signaling technology for improved communication between semiconductor devices. In one embodiment, a system contains a first semiconductor device that includes a first characterization mechanism, a control logic coupled to the first characterization mechanism, a voltage generating mechanism coupled to the control logic and a transmit buffer. The control logic adjusts at least a first voltage generated by the voltage generating mechanism based on at least a value determined by the first characterization mechanism. The first voltage is coupled to the transmit buffer to define at least a transmit voltage signal level. In an alternate embodiment, the first voltage is coupled to a receive buffer in a second semiconductor device to define at least a receive voltage signal level.

Inventors: Lau; Benedict C. (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 10/942,720

Filed: September 15, 2004

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United States Patent 7,133,463

Amirkhany, et al. November 7, 2006

Linear transformation circuits

Abstract
A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of weighted sums of the N digital data symbols. Each respective weighted sum is defined by a respective set of pre-determined weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective weighted sum of the N analog data symbols. Each respective weighted sum is defined by a respective set of pre-determined weighting values in a second matrix.

Inventors: Amirkhany; Amir (Stanford, CA), Stojanovic; Vladimir (Lexington, MA), Alon; Elad (Saratoga, CA), Zerbe; Jared LeVan (Woodside, CA), Horowitz; Mark A. (Menlo Park, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 11/213,352

Filed: August 25, 2005

Hat tip to FinzToRite for the links.