United States Patent 7,127,017
Evans, et al. October 24, 2006
Clock recovery circuit with second order digital filter
Abstract
The present invention provides a method and mechanism for regenerating the clock signal and recovering the data of a serial bit data stream. According to an embodiment, a circuit for recovering data from a serial bit stream may include a de-serializer configured for reclocking the serial bit stream using at least one reclocking signal, having a frequency with a phase, and de-serializing the serial bit stream into at least two bit streams. The circuit may further include a clock recovery loop filter having a second order filter coupled with the deserializer. The clock recovery loop filter may be configured for determining whether the de-serializer is reclocking the serial bit data stream at an optimum location and for generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal if the de-serializer is not reclocking the serial bit data stream at the optimum location. The circuit may also include a phase interpolator coupled with the clock recovery loop filter and the de-serializer, configured for generating the at least one reclocking signal in accordance with the at least one control signal.
Inventors: Evans; William P. (Catonsville, MD), Gray; C. Thomas (Apex, NC), Huss; Scott (Cary, NC)
Assignee: Rambus, Inc. (Los Altos, CA)
Appl. No.: 10/198,899
Filed: July 19, 2002
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United States Patent 7,127,003
Rajan, et al. October 24, 2006
Method and apparatus for communicating information using different signaling types
Abstract
Systems, methods, apparatuses, and arrangements enable information to be communicated across a link using different types of signaling. For example, a first type of information is communicated across a bus using a first type of signaling while a second type of information is communicated across the bus using a second type of signaling. By way of example but not limitation, in certain implementation(s) a system including a transmitting unit and a receiving unit are connected by a multi-line bus. The transmitting unit transmits data signals over the multi-line bus using differential signaling and transmits control signals over the multi-line bus using single-ended signaling. The receiving unit interprets signals received in a differential signaling format via the multi-line bus as data signals and interprets signals received in a single-ended signaling format via the multi-line bus as control signals.
Inventors: Rajan; Suresh (San Jose, CA), Best; Scott C. (Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/253,312
Filed: September 23, 2002
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United States Patent 7,126,510
Alon, et al. October 24, 2006
Circuit calibration system and method
Abstract
An integrated circuit device includes one or more calibration paths including one or more devices. A signal generator is coupled to at least one calibration path and configured to provide the calibration path with a calibration signal having known characteristics. A controller is coupled to the signal generator and the calibration path and configured to adjust the signal generator and at least one parameter associated with at least one device in the calibration path.
Inventors: Alon; Elad (Saratoga, CA), Garlepp; Bruno W. (San Jose, CA), Stojanovic; Vladimir (Stanford, CA), Ho; Andrew (Palo Alto, CA), Chen; Fred F. (San Francisco, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/015,971
Filed: December 17, 2004
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United States Patent 7,126,435
Naviasky, et al. October 24, 2006
Voltage controlled oscillator amplitude control circuit
Abstract
A voltage controlled oscillator amplitude control circuit has a voltage controlled oscillator circuit to output an oscillating signal having a controlled amplitude. It also has a control circuit to control the amplitude of the oscillating signal by providing a dominant pole, a filtering function, rectification, and a gain at a single node of the circuit.
Inventors: Naviasky; Eric H. (Ellicott City, MD), Casas; Michael A. (Pasadena, MD)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 10/948,087
Filed: September 22, 2004
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United States Patent 7,126,408
Zerbe October 24, 2006
Method and apparatus for receiving high-speed signals with low latency
Abstract
An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.
Inventors: Zerbe; Jared L. (Woodside, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 11/274,585
Filed: November 14, 2005
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United States Patent 7,126,378
Stojanovic, et al. October 24, 2006
High speed signaling system with adaptive transmit pre-emphasis
Abstract
A signaling system having first and second sampling circuits and an output driver circuit. The first sampling circuit samples a first signal generated by the output driver circuit to determine whether the first signal exceeds a first threshold. The second sampling circuit samples the first signal to determine whether the first signal exceeds a second threshold. The drive strength of the output driver circuit is adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds, and the second threshold is adjusted based, at least in part, on whether the first signal exceeds the second threshold.
Inventors: Stojanovic; Vladimir M. (Stanford, CA), Ho; Andrew C. C. (Palo Alto, CA), Bessios; Anthony (Fremont, CA), Chen; Fred F. (San Francisco, CA), Alon; Elad (Saratoga, CA), Horowitz; Mark A. (Menlo Park, CA)
Assignee: Rambus, Inc. (Los Altos, CA)
Appl. No.: 10/740,087
Filed: December 17, 2003
Hat tip to FinzToRite for the links.
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