Rambus Inc. scores patent hat trick

United States Patent 7,084,681

Green,et al. August 1, 2006

PLL lock detection circuit using edge detection and a state machine

Abstract
A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, the lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.

Inventors: Green; Michael (Carlsbad, CA); Nguyen; Nhat M. (San Jose, CA); Frans; Yohan (Palo Alto, CA); Kim; Dennis (San Francisco, CA); Bystrom; Todd (Los Altos, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 11/088,152

Filed: March 23, 2005

***

United States Patent 7,085,872

Liaw, et al. August 1, 2006

High frequency bus system

Abstract
A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

Inventors: Liaw; Haw-Jyh (Fremont, CA); Nguyen; David (San Jose, CA)

Assignee: Rambus, Inc. (Los Altos, CA)

Appl. No.: 09/839,768

Filed: April 19, 2001

***

United States Patent 7,085,906

Barth, et al. August 1, 2006

Memory device

Abstract
A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Inventors: Barth; Richard Maurice (Palo Alto, CA); Horowitz; Mark Alan (Palo Alto, CA); Hampel; Craig Edward (San Jose, CA); Ware; Frederick Abbot (Los Altos Hills, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 10/288,045

Filed: November 5, 2002

Hat tip to FinzToRite for the links.