Disputed portion of Dr. Kelley's analysis:
"Hynix has painted a picture of Rambus as a company intent on litigating its non-compatible patent portfolio starting as far back as 1993. The scope of inquiry in this trial has largely been limited to the 1998, 1999 and early 2000 period by Judge Whyte. This is the period in which Rambus first started up its patent licensing program for SDRAM. It is important to keep in mind that there were no commercial parts available for DDR or GDR during this period and SDRAM was just becoming available commercially. It is also important to keep in mind that RAMBUS only had a couple of non-compatible patents issued in 1998 and these patents were not considered strong enough on which to base a licensing program. It was not until the later half of 1999 that Rambus patent portfolio was strong enough to be used in a licensing program. Finally, it is important also to remember that RAMBUS at this time was focusing most of its engineering resources on the launch of Direct RDRAM, which had been chosen as the PC platform main memory by INTEL in the later part of 1996."
Anonymous Reader's spin:
SDRAM was introduced in production in 1996. Although some intentions to develop a PC main memory losely (sic)based on the Base and Concurrent RDRAM was begun in 1996 as a joint effort of Intel Rambus and others, no design was forthcoming that would implement what would become Direct RDRAM until many years later. The relationship of that device implementation to the 1990 '898 patent specification has a very much different history than that which you might want to portray.
Rambus' spoliation is material to the claims that are asserted, and result in material absence of information necessary to evaluate the validity of their claims. This is an intended result of Rambus' actions in purging discoverable evidence from their corporate files.
Since you're incapable of accurately portraying
Posted by Anonymous to Treowth at 8/30/2006 11:11:07 AM
Dr. Kelley's entire post linked here.
Wednesday, August 30, 2006
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1 comment:
Don't think that I don't dispute all of that bat guano.
Telling tall tales in public is the Rambus business model and a certain distortion of reality is necessary to make the tales seem true. The facts of the Rambus litigations against other implementations of bank interleaved FPM DRAM is substantially different than portrayed by both Rambus and its proponents.
As a fairly simple exercize to demonstrate that point I'd encourage the inquiring reader to compare the "clocking" specification and associated claims of US Patent #5,243,703 with the claims and specification of US Patent #5,432,823. The useful questions to ask once your reading might be "what is clock skew?" is it skew between clocks along an extended bus that must be minimized as is specified in the '703 patent (thus maximizing clock-data skew); or is it skew between clock and data as they propagate along an interconnecting bus which is attempted to be minimized in the practice of the 1992 '823 patent? Which practice is the "best method" of practicing the Rambus "invention"?
Glad we can awaken you from your solipsistic torpor and have you make some "news".
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