Tuesday, May 16, 2006

Rambus Inc. hits a triple - three patents this week

United States Patent 7,047,375

Davis, et al. May 16, 2006

Memory system and method for two step memory write operations

A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

Inventors: Davis; Paul G. (San Jose, CA); Ware; Frederick A. (Los Altos Hills, CA); Hampel; Craig E. (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 090343

Filed: March 24, 2005


United States Patent 7,046,078

Nguyen, et al. May 16, 2006

Method and apparatus for distributed voltage compensation with a voltage driver that is responsive to feedback

An integrated circuit has one or more components that operate with reference to a distributed reference voltage. A reference voltage driver produces a compensated reference voltage, and the compensated reference voltage is distributed to form the distributed reference voltage at the components. Due to factors such as trace resistance and gate leakage, the distributed reference voltage is degraded relative to the compensated reference voltage. The reference voltage driver is responsive to feedback derived from the distributed reference voltage to adjust the compensated reference voltage so that the distributed reference voltage is approximately equal to a nominal reference voltage.

Inventors: Nguyen; Huy M. (San Jose, CA); Lau; Benedict C. (San Jose, CA); Chou; Adam Chuen-Huei (San Jose, CA); Vu; Roxanne T. (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 126643

Filed: May 11, 2005


United States Patent 7,046,056

Kizer, et al. May 16, 2006

System with dual rail regulated locked loop

An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and one of a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Inventors: Kizer; Jade M. (Mountain View, CA); Lau; Benedict C. (San Jose, CA); Hampel; Craig E. (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 114433

Filed: April 26, 2005


Hat tip to FinzToRite for the links

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