Rambus - two more patents

United States Patent 7,010,658

Donnelly, et al. March 7, 2006

Transceiver with latency alignment circuitry

Abstract
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Inventors: Donnelly; Kevin (Los Altos, CA); Johnson; Mark (Los Altos, CA); Tran; Chanh (San Jose, CA); Dillon, legal representative; Nancy D. (Washington, VA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 699116

Filed: October 31, 2003

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United States Patent 7,010,642

Perego, et al. March 7, 2006

System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

Abstract
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link

Inventors: Perego; Richard E. (San Jose, CA); Sidiropoulos; Stefanos (Palo Alto, CA); Tsern; Ely (Los Altos, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 952667

Filed: September 28, 2004

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