United States Patent 7,006,932
Liaw, et al. February 28, 2006
Technique for determining performance characteristics of electronic devices and systems
Abstract
A technique for determining performance characteristics of electronic devices and systems is disclosed in one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.
Inventors: Liaw; Haw-Jyh (Fremont, CA); Yuan; Xingchao (Palo Alto, CA); Horowitz; Mark A. (Menlo Park, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 954489
Filed: October 1, 2004
Liaw, et al. February 28, 2006
Technique for determining performance characteristics of electronic devices and systems
Abstract
A technique for determining performance characteristics of electronic devices and systems is disclosed in one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.
Inventors: Liaw; Haw-Jyh (Fremont, CA); Yuan; Xingchao (Palo Alto, CA); Horowitz; Mark A. (Menlo Park, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 954489
Filed: October 1, 2004
***
United States Patent 7,005,939
Zerbe, et al. February 28, 2006
Input/output circuit with on-chip inductor to reduce parasitic capacitance
Abstract
An I/O circuit disposed on an integrated circuit substrate and having reduced parasitic capacitance. The I/O circuit includes a signal line segmented into a first signal line segment and a second signal line segment, and an inductive structure disposed between the first and second signal line segments. An on-chip termination element is coupled to the first signal line segment, and an electrostatic discharge (ESD) element is coupled to the second signal line segment.
Inventors: Zerbe; Jared L. (Woodside, CA); Stojanovic; Vladimir M. (Stanford, CA); Horowitz; Mark A. (Menlo Park, CA); Chau; Pak S. (San Jose, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 431147
Filed: May 6, 2003
Hat tip FinzToRite for the links.
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