Rambus patent issued

United States Patent 6,977,980

Chang, et al. December 20, 2005

Timing synchronization methods and systems for transmit parallel interfaces

Abstract
Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.

Inventors: Chang; Kun-Yung Ken (Los Altos, CA); Huang; Chaofeng (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 942198

Filed: August 29, 2001

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