USPO - Rambus knocks twice

United States Patent 6,963,956

Barth, et al. November 8, 2005

Apparatus and method for pipelined memory operations

Abstract
A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

Inventors: Barth; Richard M. (Palo Alto, CA); Tsern; Ely K. (Los Altos, CA); Horowitz; Mark A. (Menlo Park, CA); Stark; Donald C. (Los Altos, CA); Hampel; Craig E. (San Jose, CA); Ware; Frederick A. (Los Altos Hills, CA); Dillon; Nancy David (Washington, VA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 817781

Filed: April 2, 2004

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United States Patent 6,963,232

Frans, et al. November 8, 2005

Compensator for leakage through loop filter capacitors in phase-locked loops

Abstract
A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage across the replication capacitor is proportional to the control voltage of a voltage-controlled oscillator of the compensating phase-locked loop. A second embodiment generates the compensation current by controlling the voltage on the gate of a transistor. The gate voltage depends on charge added and subtracted by a charge pump in addition to the charge pumps in the loop filter. A third embodiment applies a leakage compensation circuit to a delay locked loop.

Inventors: Frans; Yohan (Palo Alto, CA); Nguyen; Nhat M. (San Jose, CA)

Assignee: Rambus, Inc. (Los Altos, CA)

Appl. No.: 638717

Filed: August 11, 2003

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