Rambus - Patent Grand Slam

United States Patent 6,961,862

Best, et al. November 1, 2005

Drift tracking feedback for communication channels

Abstract
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Inventors: Best; Scott C. (Palo Alto, CA); Abhyankar; Abhijit M. (Sunnyvale, CA); Chang; Kun-Yung (Los Altos, CA); Lambrecht; Frank (Mountain View, CA)

Assignee: Rambus, Inc. (Los Altos, CA)

Appl. No.: 802634

Filed: March 17, 2004

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United States Patent 6,961,831

Ware, et al. November 1, 2005

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Abstract
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one particular exemplary embodiment, the techniques may be realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections that provides access to the memory module, a second set of interface connections that provides access to the memory module, and memory access circuitry that provides memory access signals to the memoory module for selecting between a first mode wherein first and second portions of the memory core are accessible through the first and second sets of interface connections, respectively, and a second mode wherein both the first and second pertions of the memory core are accessible through the first set of interface connections.

Inventors: Ware; Frederick A. (Los Altos Hills, CA); Perego; Richard E. (San Jose, CA); Hampel; Craig E. (San Jose, CA); Tsern; Ely K. (Los Altos, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 862375

Filed: June 8, 2004

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United States Patent 6,960,952

Nguyen, et al. November 1, 2005

Configuring and selecting a duty cycle for an output driver

Abstract
The pre-driver of an output driver is calibrated so as to generate output signals having a specified duty cycle. During calibration, a closed loop is utilized to decrease the differences between the common mode voltage of the output signal and a reference voltage. Calibration data is be stored in registers so that the output driver can be readily configured for one of a plurality of signaling types, each having a respective duty cycle. Additionally, a process, voltage and temperature (PVT) detector can be utilized so that calibration of the pre-driver tracks with process, voltage and temperature variations of the integrated circuit in which the output driver resides.

Inventors: Nguyen; Huy (San Jose, CA); Lau; Benedict (San Jose, CA); Chou; Chuen-Huei (San Jose, CA)

Assignee: Rambus, Inc. (Los Altos, CA)

Appl. No.: 661862

Filed: September 11, 2003

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United States Patent 6,960,948

Kizer, et al. November 1, 2005

System with phase jumping locked loop circuit

Abstract
An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Inventors: Kizer; Jade M. (Mountain View, CA); Lau; Benedict C. (San Jose, CA); Vu; Roxanne T. (San Jose, CA); Hampel; Craig E. (San Jose, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 852650

Filed: May 24, 2004

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