Tuesday two

United States Patent 6,954,837

Woo, et al. October 11, 2005

Consolidation of allocated memory to reduce power consumption

Abstract
A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.

Inventors: Woo; Steven C. (Saratoga, CA); Batra; Pradeep (Santa Clara, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 823115

Filed: April 12, 2004

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United States Patent 6,954,095

Lau, et al. Lau October 11, 2005

Apparatus and method for generating clock signals

Abstract
A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period. A second delay element is coupled to receive the first clock signal from the delay-locked loop circuit. The second delay element also outputs a second clock signal that is delayed relative to the first clock signal by the first time period. The delay-locked loop circuit may include a phase detector to identify phase differences between the first clock signal and the reference clock signal. A third delay element may be coupled between the delay-locked loop circuit and the second delay element.

Inventors: Lau; Benedict C. (San Jose, CA); Sidiropoulos; Stefanos (Palo Alto, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 807003

Filed: March 22, 2004

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