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United States Patent 6,934,201

Ware, et al. August 23, 2005

Asynchronous, high-bandwidth memory component using calibrated timing elements

Abstract
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

Inventors: Ware; Frederick A. (Los Altos, CA); Tsern; Ely K. (Los Altos, CA); Hampel; Craig E. (San Jose, CA); Stark; Donald C. (Los Altos Hills, CA)

Assignee: Rambus Inc. (Los Altos, CA)

Appl. No.: 846220

Filed: May 14, 2004

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