To achieve its performance, XDR™ 2 incorporates:
-- Micro-threading -- a DRAM core innovation developed to increase memory system efficiency to enable DRAMs to provide more usable data bandwidth to requesting memory controllers, while minimizing power consumption;
-- Adaptive Timing -- a speed enhancement to today's XDR FlexPhase(TM) timing circuits that compensates for process, voltage and temperature variations during real-time operation;
-- Transmit Equalization -- an output circuit that minimizes the adverse system effects of reflections and attenuation that typically limit the speed of DRAM systems;
-- DRSL Signaling -- a 200mV differential signaling standard that provides superior common mode noise rejection with an on-chip terminated point-to-point topology that minimizes reflections and reduced signal transition times associated with device loading and PCB trace stubs.
The XDR™2 memory interface is available for licensing now with its appearance in products by 2007.
Update:
Techworld reports:
Rambus is looking to license the XDR2 technology now, and is gauging the interest of Samsung, the world's biggest memory chip maker, as well as Toshiba and Elpida.
Hat tip to FinzToRite of the Pinehurst Thread for the emails.
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