Rambus v. Samsung (San Jose) - Ten Rambus patents in dispute

United States Patent 5,915,105
Farmwald, et al.
June 22, 1999

Integrated circuit I/O using a high performance bus interface

Abstract
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Mountain View, CA)
Appl. No.: 979127
Filed: November 26, 1997

United States Patent 5,953,263
Farmwald, et al.
September 14, 1999

Synchronous memory device having a programmable register and method of controlling same

Abstract
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Mountain View, CA)
Appl. No.: 196200
Filed: November 20, 1998

United States Patent 6,034,918
Farmwald, et al.
March 7, 2000

Method of operating a memory having a variable data output length and a programmable register

Abstract
A method of controlling a memory device is disclosed wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to an external clock signal. In one preferred embodiment, the method may include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory device. In this preferred embodiment, the first amount of data corresponding to the first block size information is output after the number of clock cycles of the external clock transpire.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Mountain View, CA)
Appl. No.: 252997
Filed: February 19, 1999

United States Patent 6,038,195
Farmwald , et al.
March 14, 2000

Synchronous memory device having a delay time register and method of operating same

Abstract
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 9 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Mountain View, CA)
Appl. No.: 196199
Filed: November 20, 1998

United States Patent 6,067,592
Farmwald, et al.
May 23, 2000

System having a synchronous memory device

Abstract
A system for use in a computer, the system comprises a memory device and a controller or master to generate a request to provide data. The memory device includes at least one section of memory, having a plurality of memory cells, and a programmable register to store a value which is representative of a number of clock cycles of a first external clock signal to transpire before the memory device outputs data onto the bus in response to the request to provide data. The memory device may further include a plurality of output drivers and a delay lock loop circuitry wherein the delay lock loop circuitry generates a first internal clock signal using the first external clock signal. The plurality of output drivers, in response to the first internal clock signal, output data onto the bus. The plurality of output drivers output data on the bus after the number of clock cycles of the first external clock signal transpire and synchronously with respect to the first external clock signal. The delay lock loop circuitry may also generate the first internal clock signal using the first external clock signal and a second external clock signal.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Mountain View, CA)
Appl. No.: 357989
Filed: July 21, 1999

United States Patent 6,101,152
Farmwald , et al.
August 8, 2000

Method of operating a synchronous memory device

Abstract
A synchronous memory device having a plurality of memory cells and a method of operation thereof. The memory device comprising: receiver circuitry to receive a first external clock signal; and output driver circuitry, to output data after a preprogrammed number of clock cycles of the first external clock signal transpire. The data is output synchronously with respect to the first external clock signal. The method of operation comprises: receiving a request for a read operation; sensing data in a portion of the plurality of sense amplifiers in response to the request for a read operation; and outputting the data after a preprogrammed delay time transpires. The method may further include receiving an external clock signal wherein the preprogrammed time delay is representative of a fixed number of clock cycles of the external clock signal. The data is output synchronously with respect to the first external clock signal.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Mountain View, CA)
Appl. No.: 213243
Filed: December 17, 1998

United States Patent 6,324,120
Farmwald, et al.
November 27, 2001

Memory device having a variable data output length

Abstract
A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing block size information to the memory device, synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes issuing a first read request to the memory device, wherein the memory device receives the first read request synchronously with respect to a transition of the external clock signal.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 779296
Filed: February 8, 2001

United States Patent 6,378,020
Farmwald, et al.
April 23, 2002

System having double data transfer rate and intergrated circuit therefor

Abstract
A system and an integrated circuit device therefor. The integrated circuit device comprises output driver circuitry to output data onto a first external signal line. The output driver circuitry outputs a first portion of data in response to a rising edge transition of a first external clock signal. The output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal. The integrated circuit device may further include input receiver circuitry to sample data from a second external signal line. The input receiver circuitry samples a first portion of data in response to a rising edge transition of a second external clock signal. The input receiver circuitry samples a second portion of data in response to a falling edge transition of the second external clock signal.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 545648
Filed: April 10, 2000

United States Patent 6,426,916
Farmwald, et al.
July 30, 2002

Memory device having a variable data output length and a programmable register

Abstract
A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing a value which is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a read request. The method further includes providing block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes receiving the amount of data, after the number of clock cycles of the external clock signal transpire.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 796206
Filed: February 27, 2001

United States Patent 6,452,863
Farmwald, et al.
September 17, 2002

Method of operating a memory device having a variable data input length

Abstract
A method of controlling a memory device, wherein the memory device includes a plurality of memory cells. The method includes providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be input by the memory device in response to a write request. The method further includes issuing a write request to the memory device, wherein in response to the write request the memory device inputs the first amount of data corresponding to the first block size information.

Inventors: Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Assignee: Rambus Inc. (Los Altos, CA)
Appl. No.: 492982
Filed: January 27, 2000